The present invention generally relates to semiconductor memory devices and methods of producing semiconductor memory devices, and more particularly to a semiconductor memory device which has a fin type stacked capacitor which is used as a charge storage capacitor and a method of producing such a semiconductor memory device.
Presently, a stacked capacitor or a trench capacitor is often used as a charge storage capacitor of a dynamic random access memory (DRAM).
Such charge storage capacitors occupy a relatively small area on a substrate but can realize a relatively large capacitance. Hence, it is expected that such charge storage capacitors can improve the integration density and the signal-to-noise (S/N) ratio of the DRAM at the same time. However, further improvements of such charge storage capacitors are still required.
Compared to the trench capacitor, the production of the stacked capacitor is simple. In addition, the reproducibility of the stacked capacitor is better compared to that of the trench capacitor.
Recently, a DRAM having the so-called fin type stacked capacitor is proposed in Ema et al., "3-Dimensional Stacked Capacitor Cell For 16M and 64M DRAMs", International Electron Devices Meeting, pp.592-595, December 1988. The fin type stacked capacitor includes electrodes and dielectric films which extend in a fin shape in a plurality of stacked layers.
Next, a description will be given of a method of producing the DRAM having the fin type stacked capacitor, by referring to FIGS. 1 through 11.
In FIG. 1, a selective thermal oxidation (for example, local oxidation of silicon (LOCOS)) which uses an oxidation resistant mask such as a Si.sub.3 N.sub.4 layer is employed to form a field insulator layer 2 on a p-type Si semiconductor substrate 1. The field insulator layer 2 is made of SiO.sub.2 and has a thickness of 3000 .ANG., for example.
Then, the oxidation resistant mask is removed to expose an active region of the p-type Si semiconductor substrate 1.
A gate insulator layer 3 which is made of SiO.sub.2 and has a thickness of 150 .ANG., for example, is formed on the substrate surface by a thermal oxidation.
A polysilicon layer having a thickness of 2000 .ANG., for example, is formed on the gate insulator layer 3 and the field insulator layer 2 by a chemical vapor deposition (CVD).
The polysilicon layer is doped by a p-type impurity by carrying out a thermal diffusion which uses POCl.sub.3 as a source gas.
Next, a resist process of a normal photolithography technique and a reactive ion etching (RIE) using CCl.sub.4 +O.sub.2 as an etching gas are used to pattern the polysilicon layer and form gate electrodes 4.sub.1 and 4.sub.2 which correspond to word lines.
The gate electrodes 4.sub.1 and 4.sub.2 are used as a mask and As ions are implanted by an ion implantation. In addition, a thermal process is carried out for activation, so as to form an n.sup.+ -type source region 5 and an n.sup.+ -type drain region 6. The n.sup.+ -type source region 5 corresponds to a bit line contact region, and the n.sup.+ -type drain region 6 corresponds to a storage electrode contact region. For example, the As ions are implanted with a dosage of 1.times.10.sup.15 cm.sup.-2.
Next, as shown in FIG.2, an interlayer insulator 7 is formed by a CVD. The interlayer insulator 7 is made of SiO.sub.2 and has a thickness of 1000 .ANG., for example. The interlayer insulator 7 may be made of Si.sub.3 N.sub.4.
A resist process of a normal photolithography technique and a RIE using CHF.sub.3 +O.sub.2 as an etching gas are carried out to selectively etch the interlayer insulator 7 and form a bit line contact hole 7A.
Next, as shown in FIG.3, a CVD is carried out to form a polysilicon layer having a thickness of 500 .ANG., for example.
In order to make the polysilicon layer conductive, an ion implantation is carried out to implant As ions into the polysilicon layer with a dosage of 1.times.10.sup.17 cm.sup.-2 and an acceleration energy of 50 keV.
A CVD is carried out to form a WSi.sub.2 layer having a thickness of 1000 .ANG., for example.
A resist process of a normal photolithography technique and a RIE using CCl.sub.4 +O.sub.2 as an etching gas are carried out to pattern the polysilicon layer and the WSi.sub.2 layer to form a bit line 12.
Next, as shown in FIG.4, an etching protection layer 13 having a thickness of approximately 1000 .ANG., for example, is formed by a CVD.
Then, as shown in FIG.5, a SiO.sub.2 layer 14 and a polysilicon layer 15 are formed by a CVD. For example, the SiO.sub.2 layer 14 and the polysilicon layer 15 respectively have a thickness of 1000 .ANG..
In order to make the polysilicon layer 15 conductive, an ion implantation is carried out to implant As ions with a dosage of 4.times.10.sup.15 cm.sup.-2 and an acceleration energy of 50 keV.
A SiO.sub.2 layer 16 and a polysilicon layer 1 are formed by a CVD. In this case, the SiO.sub.2 layer 16 and the polysilicon layer 17 respectively have a thickness of approximately 1000 .ANG..
In order to make the polysilicon layer 17 conductive, an ion implantation is carried out to implant As ions with a dosage of 4.times.cm.sup.-2 and an acceleration energy of 50 keV.
An SiO.sub.2 layer 18 is formed by a CVD. For example, the SiO.sub.2 layer 18 has a thickness of approximately 1000 .ANG..
In FIG.6, a resist process of a normal photolithography technique and a RIE are carried out to selectively etch the SiO.sub.2 layer 18 and the like. As a result, a storage electrode contact window 7B is formed. This storage electrode contact window 7B extends from a top surface of the SiO.sub.2 layer 18 to a surface of the n.sup.+ -type drain region 6. The etching gas is desirably CHF.sub.3 +O.sub.2 for SiO.sub.2, CCl.sub.4 +O.sub.2 for polysilicon, and CHF.sub.3 +O.sub.2 for Si.sub.3 N.sub.4.
Next, as shown in FIG.7, a polysilicon layer 19 is formed by a CVD. In this case, the thickness of the polysilicon layer 19 is approximately 1000 .ANG..
In order to make the polysilicon layer 19 conductive, an ion implantation is carried out to implant As ions with a dosage of 4.times.10.sup.15 cm.sup.-2 and an acceleration energy of 50 keV.
In FIG.8, a resist process of a normal photolithography and RIEs using CCl.sub.4 +O.sub.2 as the etching gas for polysilicon and using CHF.sub.3 +O.sub.2 as the etching gas for SiO.sub.2 are carried out to pattern the polysilicon layer 19, the SiO.sub.2 layer 18, the polysilicon layer 17, the SiO.sub.2 layer 16 and the polysilicon layer 15 and to form a storage electrode pattern.
Next, as shown in FIG.9, the structure shown in FIG.8 is submerged into a hydrofluoric acid such as HF:H.sub.2 O =1:10, so as to remove the SiO.sub.2 layers 18, 16 and 14. By carrying out this process, a fin-shaped storage electrode made of polysilicon is formed in a plurality of layers, that is, levels.
In addition, as shown in FIG.10, a thermal oxidation is carried out to form a dielectric layer 20 having a thickness of 100 .ANG., for example, on each surface of the polysilicon layers 19, 17 and 15. As an alternative, it is also possible to carry out a CVD in order to form a dielectric layer which is made of Si.sub.3 N.sub.4 and has a thickness of 100 .ANG., for example, on each surface of the polysilicon layers 19, 17 and 15.
Then, as shown in FIG.11, an opposed electrode (cell plate) 21 which is made of polysilicon and has a thickness of 1000 .ANG., for example, is formed by a CVD. In addition, the opposed electrode 21 is doped by a p-type impurity by carrying out a thermal diffusion using POCl.sub.3 as a source gas. Further, the opposed electrode 21 is patterned by a RIE using CCl.sub.4 +O.sub.2 as an etching gas.
Although not shown in FIG.11, a passivation layer, a bonding pad, an underlayer interconnection for reducing the resistance of the word line, other interconnections and the like are formed to complete the DRAM.
The DRAM which is produced in the above described manner includes a fin type stacked capacitor which has a large capacitance. Hence, even when the size of the fin type stacked capacitor is made extremely small, it is still possible to obtain a sufficiently large information signal and a satisfactory S/N ratio is obtainable. In addition, the resistance against the .alpha.-ray is large.
When the fin type stacked capacitor having the above described structure is used to produce a 64 Mbit/chip DRAM, for example, the memory cell becomes extremely fine and various difficulties are encountered.
First, the polysilicon layers 19, 17 and 15 which become the fin-shaped storage electrode of the charge storage capacitor easily disconnect from the polysilicon layer 19 which forms a support part at the core of the capacitor. When the fin-shaped storage electrode disconnects and falls from the support part, the memory cell becomes defective, and in addition, the disconnected fin-shaped storage electrode in most cases act as a foreign particle which damages other memory cells.
Second, when forming the support part (a part of the polysilicon layer 19), the storage electrode contact window 7B which penetrates a plurality of layers is formed. But when forming the storage electrode contact window 7B, the storage electrode contact window 7B must be aligned with respect to the plurality of layers. Such an alignment is extremely difficult to make, and as a result, it is necessary to provide a large alignment margin.
Third, the area occupied by the charge storage capacitor on the substrate is not increased considerably. This is because the support part becomes relatively large compared to the fin-shaped storage electrode as the size of the charge storage capacitor is reduced. Consequently, the rate with which the capacitance is increased by the fin-shaped storage electrode decreases as the size of the charge storage capacitor is reduced.